(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device which is capable of suppressing defects that may occur due to a remaining polymer, since polymer produced by a previous etching process can be removed during an ashing process for removing a photoresist on a surface of the device.
(b) Description of the Related Art
A photolithography process for patterning a semiconductor device is one of the most important processes among various manufacturing processes of semiconductor devices. According to a typical photolithography patterning process, photoresist application, soft baking, exposure, baking (“post-exposure” baking), and development processes are sequentially performed. After such a photolithography patterning process, an ashing process is performed for removing the photoresist without causing damage to the semiconductor device, generally using an O2 plasma.
A conventional photolithography and ashing processes will be described in detail with reference to FIG. 1A to FIG. 1D, with an example of a method of fabricating a metal-insulator-metal (MIM) capacitor.
A capacitor used in an analog circuit (for example, a CMOS analog logic circuit) usually has a polysilicon-insulator-polysilicon (PIP) structure or the MIM structure. Different from a MOS capacitor or a junction capacitor, such a capacitor is typically bias-independent, and thus high precision is required.
One may select either the PIP structure or the MIM structure, depending on the target use. For example, the MIM structure is usually used for a semiconductor device intended to operate at a high frequency. In more detail, since the characteristics of the high frequency device are quite dependent on RC delays, the MIM structure using a metal having good electrical characteristics is often selected for such a high frequency device.
Referring to FIG. 1A, a barrier metal layer 13, a metal layer 15, and an anti-reflection coating (ARC) layer 17 are sequentially deposited on an insulation layer 11 in a semiconductor substrate (generally having one or more lower structures below the insulation layer 11, not shown) so as to form a lower metal line. An insulation layer 19 such as a silicon nitride layer is formed on the ARC layer 17. Further, titanium (Ti), titanium nitride (TiN), or a Ti/TiN bilayer is deposited thereon as an upper electrode by a sputtering process so as to form an upper metal layer 21.
Subsequently, an upper electrode photoresist pattern 23 is formed by depositing (usually by spin-coating) a photoresist layer over the entire silicon substrate and then patterning the photoresist layer. Then, a reactive ion etching (RIE) process is performed using the upper electrode photoresist pattern 23 as an etching mask. By the etching process, exposed regions of the upper metal layer 21 and the insulation layer 19 are removed so as to form the upper electrode. A polymer 1 (refer to FIG. 1B) may form on exposed surfaces of the device during such an etching process.
Referring to FIG. 1B, oxygen (O2) gas is inserted into a vacuum process chamber, and then high frequency power (i.e., an RF power) is applied thereto so as to generated a white glow (plasma) discharge. During the ashing process for removing the photoresist pattern 23, O radicals generated by the O2 plasma react with the photoresist so as to form reaction products, and the reaction products are exhausted or removed from the chamber by vacuum. Subsequently, a wet cleaning process is performed in order to remove the polymer 1 produced during the etching of the upper metal layer 21.
However, as shown in FIG. 1B, the polymer 1 produced in the previous etching process may react or otherwise combine with the photoresist and remain on the ARC layer 17. Although the ashing with O2 plasma shows a good ashing rate and good removability, plasma damage may be caused to the device. Furthermore, surface hardening may occur during the ashing process, which may cause adverse effects.
Referring to FIG. 1C, in order to form a lower electrode, another photoresist layer (not shown) is formed by applying a photoresist over the entire structure having the upper electrode. Subsequently, the photoresist layer is patterned such that a lower electrode photoresist pattern 25 partially exposes the lower metal line. At this time, a region 3 may be formed at the lower electrode photoresist pattern 25 by the polymer 1 remaining from the previous processes. The region 3 may function as a partial etch mask, as is explained with regard to FIG. 1D.
Now referring to FIG. 1D, a reactive ion etching process is performed using the lower electrode photoresist pattern 25 as an etching mask. By the etching process, exposed regions of the ARC layer 17, the metal layer 15, the barrier metal layer 13, and the interlayer insulation layer 11 are removed to a predetermined width so as to form the lower electrode. When the region 3 occurs at the lower electrode photoresist pattern 25 in the previous process, it negatively affects the etching process for forming the lower electrode (e.g., by blocking exposure of the ARC layer 17 from the etch process for some period of time). Thus, an unetched region 5 may also occur at one or more layers in or under the lower electrode (e.g., the metal layer 15, the barrier metal layer 13, and/or the insulation layer 11).
As described above, according to the art, a polymer produced during a metal etching process may not be fully removed, and may remain through subsequent processes, thereby resulting in a negative effect such as a partial mask region. In this case, a process margin for a subsequent process may deteriorate, and the yield of semiconductor devices may also deteriorate.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not form prior art or other information that is already known in this or any other country to a person of ordinary skill in the art.